Embodiments of the present disclosure relate to semiconductor devices and, more particularly, to semiconductor devices including vertical transistors, electronic systems including the same and methods of manufacturing the same.
In fabrication of semiconductor devices, various technologies for more integrating elements such as transistors in a limited area of a semiconductor substrate have been proposed to improve the throughput of the semiconductor devices. For example, dynamic random access memory (DRAM) technologies have been developed to realize a unit memory cell including a single cell transistor and a single cell capacitor in a unit area of about 4F2 (“F” denotes a minimum feature size). In response to the above requirements, planar transistors used as the cell transistors have been increasingly replaced with vertical transistors.
Each of the vertical transistors may be configured to include a drain region and a source region respectively disposed in an upper portion (or a lower portion) and a lower portion (or an upper portion) of an active pillar, and a gate electrode disposed on a sidewall of the active pillar between the drain region and the source region. When the vertical transistors are employed as the cell transistors of the DRAM devices, the drain regions in the active pillar may be electrically connected to bit lines and the source regions in the active pillars may be electrically connected to the cell capacitors acting as data storage elements. Thus, one of the cell capacitor and the bit line may be formed in a bulk region of semiconductor substrate. For example, when the drain regions of the vertical transistors are formed in the lower portions of the active pillars, the bit lines may be formed in the semiconductor substrate to have buried structures.
In the event that the bit lines of the DRAM devices are buried in the semiconductor substrate, it may be difficult to form the buried bit lines because the buried bit lines should be buried in the semiconductor substrate and should be electrically connected to the drain regions. That is, complicated processes may be required to electrically connect the buried bit lines to the drain regions of the active pillars.